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Computational lithography (also known as computational scaling) is the set of mathematical and algorithmic approaches designed to improve the resolution attainable through photolithography. Computational lithography has come to the forefront of photolithography in 2008 as the semiconductor industry grappled with the challenges associated with the transition to 22 nanometer CMOS process technology and beyond. ==Context: industry forced to extend 193nm deep UV photolithography== The periodic enhancement in the resolution achieved through photolithography has been a driving force behind Moore's Law. Resolution improvements enable printing of smaller geometries on an integrated circuit. The minimum feature size that a projection system typically used in photolithography can print is given approximately by: : where is the minimum feature size (also called the critical dimension). is the wavelength of light used. is the numerical aperture of the lens as seen from the wafer. (commonly called ''k1 factor'') is a coefficient that encapsulates process-related factors. Historically, resolution enhancements in photolithography have been achieved through the progression of stepper illumination sources to smaller and smaller wavelengths — from "g-line" (436 nm) and "i-line" (365 nm) sources based on mercury lamps, to the current systems based on deep ultraviolet excimer lasers sources at 193 nm. However the progression to yet finer wavelength sources has been stalled by the intractable problems associated with extreme ultraviolet lithography and x-ray lithography, forcing semiconductor manufacturers to extend the current 193 nm optical lithography systems until some form of next-generation lithography proves viable (although 157 nm steppers have also been marketed, they have proven cost-prohibitive at $50M each). Efforts to improve resolution by increasing the numerical aperture have led to the use of immersion lithography. As further improvements in resolution through wavelength reduction or increases in numerical aperture have become either technically challenging or economically unfeasible, much attention has been paid to reducing the k1-factor. The k1 factor can be reduced through process improvements, such as phase-shift photomasks. These techniques have enabled photolithography at the 32 nanometer CMOS process technology node using a wavelength of 193 nm (deep ultraviolet). However, with the ITRS roadmap calling for the 22 nanometer node to be in use by 2011, photolithography researchers have had to develop an additional suite of improvements to make 22 nm technology manufacturable. While the increase in mathematical modeling has been underway for some time, the degree and expense of those calculations has justified the use of a new term to cover the changing landscape: computational lithography. 抄文引用元・出典: フリー百科事典『 ウィキペディア(Wikipedia)』 ■ウィキペディアで「Computational lithography」の詳細全文を読む スポンサード リンク
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